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| rev.1.00, june.13.2003, page 1 of 70 HD66779 366-channel source driver for 262,144-color displays (64 grayscale) for amorphous silicon, low-temperature poly-silicon tft panels rejxxxxxxx-xxxxz rev.1.00 june.13.2003 description ......................................................................................................... 4 features ......................................................................................................... 5 block diagram .................................................................................................... 6 block function.................................................................................................... 7 (1) external display interface (rgb ?i/f) ................. .......................... .......................... ............. 7 (2) control circuit ............................................................................................................ ............ 7 (3) grayscale voltage generation circ uit ........................ .......................... ........................ ......... 7 (4) timing generator........................................................................................................... ........ 7 (5) lcd driver circuit ......................................................................................................... ....... 7 (6) vcom oscillation generator circuit ...................... .......................... .......................... ............. 7 (7) level shifter circuit ...................................................................................................... .......... 7 (8) system interface clock synchronized serial circuit .................. .................... .......................... 8 pin function ......................................................................................................... 9 pad arrangement................................................................................................. 16 pad coordinate.................................................................................................. 17 instruction ......................................................................................................... 19 index: ir...................................................................................................................... ................ 19 power save, color control: r01h................................................................................................ .19 border color control (1): r02h ... .............................................................................................. ... 20 border color control (2): r03h ... .............................................................................................. ... 20 lcd driving waveform control, source ou tput control: r04h .................................................... 21 gate non overlap control, border color control: r05h............................................................ 22 display signal select control, flame control 1: r06h ............................................................... 23 instruction list .................................................................................................... 26
HD66779 rev.1.00, june.13.2003, page 2 of 70 reset function .................................................................................................... 27 lcd signal timing control function ................................................................ 28 lcd signal timing control function ................................................................ 29 power control function...................................................................................... 30 power control function (poc) .......... ......................................................................................... .. 30 poc / vcomg / lsenr/l output contro l................................................................................. 31 interface ......................................................................................................... 32 rgb interface timing 1 (366ch x 2 / with border) .... .......................... .......................... ............. 32 rgb interface timing 2 (360ch x 2 / with out border) .................. .................... .......................... 33 lcd panel interface timing 1 (366ch x 2 / with border) ............................................................ 34 lcd panel interface timing 2 (366ch x 2 / without border) ....................................................... 35 de transfer mode 1 (366ch x 2 / with border) ........................................................................... 36 de transfer mode 2 (366ch x 2 / without border) ...................................................................... 37 lcd panel interface timing while de transf er mode 1 (with border)........................................ 38 lcd panel interface timing while de transfer mode 2 (without border)................................... 39 lcd panel interface timing while de tr ansfer mode 3 ............................................................... 40 serial peripheral interface (spi) function .......................................................... 41 settings for data shift direction/boder mode.................................................... 43 lcd ac drive.................................................................................................... 44 lcd display signal control............................................................................... 45 grayscale amplifier configuration .................................................................... 46 the relationship between input data and ou tput level .................................... 47 voltage calculation formula (positive po larity) ........................................................................... 48 voltage calculation formula (negative po larity) ......................................................................... 49 system configuration examples......................................................................... 50 system configuration example 1 ................................................................................................ 5 0 system configuration example 2 ................................................................................................ 5 1 system configuration example 3 ................................................................................................ 5 2 system configuration example 4 ................................................................................................ 5 3 system configuration example 5 ................................................................................................ 5 4 vcom generation ................................................................................................ 55 voltage application and insulation sequence. .................................................... 56 absolute maximum ratings ............................................................................... 57 HD66779 rev.1.00, june.13.2003, page 3 of 70 electrical characteristics ..................................................................................... 58 dc characteristics.... ......................... .......................... .......................... ................... ......... ........... 58 serial peripheral interface timing ch aracteristics ..... .......................... ......................... .............. 60 reset timing characteristics............ .......................... .......................... .......................... ......... .... 60 rgb interface timing characteristics .......................... .......................... .......................... ............. 60 switching characteristics .................. .......................... .......................... ................... ............. ....... 61 lcd driver output characteristics.............................................................................................. .. 61 notes to electrical characteristics ...................................................................... 62 timing diagram ................................................................................................................. .......... 65 serial peripheral interface operation ......................... ................... .......................... .................... 65 reset operation ................................................................................................................ ........... 65 interfacing operation.......................................................................................................... ......... 66 switching operation ......................... .......................... .......................... ................... ............ ........ 66 lcd driver output characteristics ............................................................................................. 6 7 HD66779 rev.1.00, june.13.2003, page 4 of 70 description the HD66779 is a channel source driver lsi compliant to 366-channel graphics display on tft lcd in 262,144 colors. with an internal timing controller, the HD66779 can adjust lcd signals to an optimum timing. the HD66779 incorporates 18-bit rgb interface (vsync, hsync, dotclk, enable, and pd 17-0) for moving picture display. as a system interface with microcomputer, the HD66779 adopts a serial interface which enables high quality display and low power consumption through instruction settings. the HD66779 enables precise management of power by software, which makes this lsi the best solution for medium or small-sized portable products such as digital cellular phones or pda supporting www browser, where long battery life is major concern. HD66779 rev.1.00, june.13.2003, page 5 of 70 features ? 366-channel output built-in liquid-crystal display driver circuit ? 6-bit (grayscale data) x rgb data ? 18-bit built-in rgb interface for moving picture display: vsync, hsync, dotclk, enable, pd17-0 ? multicolor display: 262,144 colors simultaneously available ? built-in timing controller: adjust lcd signals to an optimized timing ? 10 reference power supply voltage pins enables optimum compensation according to liquid crystal characteristics ? system interface: serial peripheral interface (spi) ? border display: 6-channel border display by mode setting ? cascade connection ? reversible source-driver shift direction ? built-in level shift circuit for lcd signals ? built-in vcom generating circuit ? raster-row inversion drive ? high-speed operation: 10mhz max. ? power supply voltage range input voltage level logic power supply voltage: vcc = 2.5v ~ 3.6v source driver power supply voltage: ddvdh = 3.5v ~ 5.5v gate driver power supply voltage: vgh ?vgl = 16v ~ 35v vgh ?agnd = 8v ~ 20v vgl ?agnd = -15v ~ -8v output voltage level output for lcd display panel: sout1-4r/l = vgl ~ vgh lsout1-4r/l, m = gnd ~ vcc source output s1 to s366 = agnd + 0.3 ~ ddvdh ? 0.3 vcoms output voltage vcoms = agnd ~ ddvdh HD66779 rev.1.00, june.13.2003, page 6 of 70 block diagram system interface clock synchronized serial (spi) control circuit external display interface m/s control index register adjustment circuit grayscale voltage generating circuit lcd display signal timing adjusting circuit lcd drive circuit latch circuit latch circuit m ac drive circuit vcom oscillation generating circuit level shifter circuit vcc gnd vgh vgl vcom r chreg bmode3 bp shl vsync hsync dotclk enable dpl epl pd17 to pd0 ei 01/2 reset tests tes tx testgxl/ r ts1 to 0 bmode 2 vref0p to 4p vref0n to 4n ddvdh agnd s1 to 366 vcomrc vcoms mr/l sout1r/l sout2r/l sout3r/l sout4r/l lsout1r/l lsout2r/l lsout3r/l lsout4r/l v0 to 63 vcom g poc testps sdi scl cs im1, im (id) gif 0/1 sdt 0/1 clw 0/1 ga 0n lsenl/ r bmode 1 ssmd1 HD66779 rev.1.00, june.13.2003, page 7 of 70 block function (1) external display interface (rgb ?i/f) the HD66779 incorporates rgb-i/f as an external interface for moving picture display. in the rgb-i/f mode, the HD66779 operates in synchronization with externally supplied signals (vsync, hsync, and dotclk), and takes in data according to data enable signal (enable). see ?rgb interface timing? for details. the correspondence between input and output data is as follows. input data pd 17 pd 16 pd 15 pd 14 pd 13 pd 12 pd 11 pd 10 pd 9 pd 8 pd 7 pd 6 pd 5 pd 4 pd 3 pd 2 pd 1 pd 0 rgb assignment output pins r5 r4 r3 r2 r1 g5 g4 g3 g2 g1 b5 b4 b3 b2 b1 b0 g0 r0 s (3n+1) s (3n+2) s (3n+3) * n = 0 to 121 (2) control circuit generate internal control signal from each signal. (3) grayscale voltage generation circuit generates positive-polarity 64 grayscales and negative-polarity 64 grayscales by dividing external input voltage with resistors to enable display in 262,144 colors. see the ?grayscale amplifier configuration? for details. (4) timing generator generate timing signals for lcd display operation. (5) lcd driver circuit the lcd driver circuit comprises a 366-source-output (s1-s366) driver. line-latch display pattern data and output drive waveform. the shift direction of source output is changeable, i.e. (s1, s2, s3) to (s364, s365, s366) or (s364, s365, s366) to (s1, s2, s3), depending on the assembly. (6) vcom oscillation generator circuit generate oscillation signal vcoms to further generate vcom, which is supplied to the tft common electrode. alternate at amplitude of either vcomr or gnd level depending on the ac frequency signal. (7) level shifter circuit change operation voltage level from that of logic circuit ?vcc to gnd? to that of gate drive circuit ?vgh to vgl?. HD66779 rev.1.00, june.13.2003, page 8 of 70 (8) system interface clock synchronized serial circuit interfacing with a microcomputer enables register setting for each mode setting. HD66779 rev.1.00, june.13.2003, page 9 of 70 pin function signals number of pins i/o connected to function ddvdh 1 i power supply power supply for the source driver. ddvdh = +3.5 ~ +5.5v. make sure vgh ddvdh vcc. agnd 1 i power supply grand for the source driver. agnd = 0v. vcc 1 i power supply power supply for the logic. vcc = +2.5v ~ +3.6v make sure vgh ddvdh vcc. gnd 1 i power supply grand for the logic. gnd = 0v. vgh 1 i power supply power supply for a level shifter. vgh = +8.0v ~+20v make sure vgh ddvdh vcc. vgl 1 i power supply power supply for a level shifter. vgl = ?15v ~ ? 8.0v vcomr 1 i power supply input high level of vcoms vcomrc 1 o stabilizing capacitor output high level of vcoms vcoms 1 o capacitor amplitude signal for alternating operation. serve as a power supply for the electrode pair (common) of tft display by coupling with an external circuit. reset 1 i mpu or external cr circuit reset pins. initialized while ?low?. power-on reset required after turning on the power supply. vref0p-4p vref0n-4n 10 i power supply power supply for compensation. must observe the following relationships when supplying voltage. ddvdh-0.3v vref0p>vref1p>vref2p>vref3p> vref4p agnd+0.3v ddvdh-0.3v vref0n > vref1n > vref2n> vref3n > vref4n agnd +0.3v ddvdh-1.0v vref1p,vref1n vref3p, vreff3n gnd + 1.0v test1, 5-15 testm2 testsm2 14 i gnd test pins. must be fixed to gnd level. vtes,vtest, comp, ts1-0 comm 6 o open test pins. must be disconnected. vcommh, vcomhc, veq, vcomc 4 o open test pins. must be disconnected. HD66779 rev.1.00, june.13.2003, page 10 of 70 signals number of pins i/o connected to function testg1-3r testg1-3l 6 o open test pins. must be disconnected. tests 1 o open test pin. must be disconnected. testps test4 2 i vcc test pin. must be fixed to the vcc level. s1 ~ s366 366 o lcd output voltage applied to liquid crystal. the shift direction of source output is changeable with shl pin. shl = ?high?: (s1, s2, s3) to (s364, s365, s366) shl = ?low?: (s364, s365 , s366) to (s1, s2, s3) bmode1 1 i gnd or vcc select border mode. bmode1 = ?higih?: border display (360ch display + 6-ch border) bmode1 = ?low?: no border display (360ch) border display lasts 320h. bmode2 1 i gnd or vcc select pins used for the border mode. bmode2 = ?high?: right side bmode2 = ?low?: left side bmode3 1 i gnd or vcc select the border color while using de transfer mode. with normally white display, bmode3 = ?high?: black bmode3 = ?low?: white while using de transfer mode, 6-channel (2rgb) border color is made on the left/right sides only. poc 1 i mpu or vcc power control signal. poc = ?high?: normal mode poc = ?low?: power control mode when poc = ?l?, non-lit display is shown (white display in normally white mode). for details, see ?power control mode?. the initialized value for the border is ?1? for all. shl 1 i gnd or vcc control the shift direction of display data. shl = ?high?: (s364,s365 ,s366) to (s1,s2,s3) shl = ?low?: (s1,s2,s3) to (s364, s365, s366) vcom generator enable signal vcomg vcom output h vcom generating vcomg 1 i gnd or vcc l gnd chreg 1 i gnd or vcc switch between the pin setting and the register setting. chreg = ?high?: register setting is valid. all pin settings are made invalid. chreg = ?low?: the settings for pins, poc, pos, bp,gaon, gifi-0, clw1-0, sdt1-0 are valid. HD66779 rev.1.00, june.13.2003, page 11 of 70 signals number of pins i/o connected to function vsync 1 i mpu frame synchronizing signal. ?low? active signal. hsync 1 i mpu line synchronizing signal. ?low? active signal. dotclk 1 i mpu dot clock signal. the timing for reading data is selected with dpl pin. pd17 ~ pd0 18 i mpu input display data of 6-bit (grayscale) x 3 pixels. as data is transferred with these pins, u nused pins must be fixed to either ?vcc? or ?gnd? level. pd17 to pd12 pd11 to pd6 pd5 to pd0 msblsb msblsb msblsb s (3n+1) s (3n+2) sn (3n+3) * n = 0 to 121 data enable signal. epl enable data write l l valid l h invalid h l invalid enable (de) 1 i mpu h h valid start pulse signal. shl signal controls the switch between input and output. when the signal is used as ou tput, output the h pulse and start up the next raster-row driver. shl ei01 ei02 l input output h output input ei01/2 2 i/o HD66779 when using ei0/2 as input, use as start pulse input or fix to vcc level. dpl 1 i gnd or vcc set the polarity of dotclk pin while receiving data (pd17 to 0). dpl = ?low?: read data at dotclk falling edge. dpl = ?high?: read data at dotclk rising edge. epl 1 i gnd or vcc set the polarity of enable pin while receiving data (pd17 to 0). epl = ?l?: when enable = ?l?, data write is valid. when enable = ?h?, data write is invalid. epl = ?h?: when enable = ?l?, data write is invalid. when enable = ?h?, data write is valid. HD66779 rev.1.00, june.13.2003, page 12 of 70 signals number of pins i/o connected to function bp 1 i gnd or vcc set a back porch during vertical period. bl = ?l?: back porch = 4 receive data (pd17 to 0) after 4h after vsync assertion bl = ?h?: back porch = 8 receive data (pd17 to 0) after 8h after vsync assertion * in the de transfer mode (ssm d1 = ?h?), bp setting is made invalid. set the delay amount of the output signal from sout2/ sout3. delay amount clw1 clw0 delay time 5mhz (e.g.) l l 0 s 0 clock l h 2. 0 s 10clocks h l 4. 0 s 20 clocks h h 6. 0 s 30 clocks clw0/1 2 i gnd or vcc * the delay time changes depending on the frequency of dotclk. set the delay amount of source output. delay amount sdt1 sdt0 delay time 5mhz (e.g.) l l 2. 0 s 10 clocks l h 3.0 s 15 clocks h l 4. 0 s 20 clocks h h 5. 0 s 25 clocks sdt0/1 2 i gnd or vcc * the delay time changes depending on the frequency of dotclk. ml mr 2 o power supply or open ac cycle clock signal. (output logic level) ml and mr output a same signal. due to chip layout, ml and mr are arranged on the left and right sides respectively. use either one of them and left the other open. sout1l sout1r 2 o gate circuit frame pulse signal for l cd display. (level shifter output with operational voltage amplitude vgh-vgl). sout1l and sout1r output a same signal. due to chip layout, sout1l and sout1r are arranged on the left and right sides respectively. use either one of them and left the other open. the lsel/lser pin function enables to halt output from either one or both. HD66779 rev.1.00, june.13.2003, page 13 of 70 signals number of pins i/o connected to function sout2r sout2l 2 o gate circuit line cycle clock signal for lcd display. (level shifter output with operational voltag e amplitude vgh-vgl). the line cycle mode is changeable by the combination of gate interface output select signal pins (gif0, gif1). sout2l and sout2r output a same signal. due to chip layout, sout2l and sout2r are arranged on the left and right sides respectively. use either one of them and left the other open. the lsel/lser pin function enables to halt output from either one or both. sout3r sout3l 2 o gate circuit signal for lcd display. (level shifter output with operational voltage amplitude vgh-vgl). the switch between line cycle mode and gate-all-on control signal is made by the combination of gate interface output select signal pins (gif0, gif1). sout3l and sout3r output a same signal. due to chip layout, sout3l and sout3r are arranged on the left and right sides respectively. use either one of them and left the other open. the lsel/lser pin function enables to halt output from either one or both. sout4r sout4l 2 o gate circuit signal for lcd display. (level shifter output with operational voltage amplitude vgh-vgl). the switch between gate off control signal and gate-all-on control signal is made by the combination of gate interface output select signal pins (gif0, gif1). sout4l and sout4r output a same signal. due to chip layout, sout4l and sout4r are arranged on the left and right sides respectively. use either one of them and left the other open. the lsel/lser pin function enables to halt output from either one or both. lsenr 1 i gnd or vcc level shifter enable signal. lsenr = ?h?: sout1/2/3/4r = level shifter output lsenr = ?l?: sout1/2/3/4/r = ?vgl? output lsenl 1 i gnd or vcc level shifter enable signal. lsenl = ?h?: sout1/2/3/4l = level shifter output lsenl = ?l?: sout1/2/3/4l = ?vgl? output select display signal. gif1 gif0 l/sout2 l/sout3 l/sout4 l l line cycle clock 1 line cycle clock 2 open l h line cycle clock 1 line cycle clock 2 gate off signal h l line cycle clock 1 line cycle clock 2 gate all on gif0/1 2 i mpu or vcc or gnd h h line cycle clock 3 gate all on gate off signal HD66779 rev.1.00, june.13.2003, page 14 of 70 signals number of pins i/o connected to function lsout1r lsout1l 2 o gate circuit frame pulse signal fo r lcd display. (output logic level) lsou1l and lsout1r output a same signal. due to chip layout, lsout1l and lsout1r are arranged on the left and right sides respectively. use either one of them and left the other open. lstou2r lsout2l 2 o gate circuit line cycle clock signal for lcd display. (output logic level) the line cycle mode is changeable by the combination of gate interface output select signal pins (gif0, gif1). lsout2l and lsout2r output a same signal. due to chip layout, lsout2l and lsout2r are arranged on the left and right sides respectively. use either one of them and left the other open. lsout3r lsout3l 2 o gate circuit signal for lcd display. (output logic level). the switch between line cycle mode and gate-all-on control signal is made by the combination of gate interface output select signal pins (gif0, gif1). sout3l and sout3r output a same signal. due to chip layout, sout3l and sout3r are arranged on the left and right sides respectively. use either one of them and left the other open. lsout4r lsout4l 2 o gate circuit signal for lcd display. (output logic level). the switch between gate off control signal and gate-all-on control signal is made by the combination of gate interface output select signal pins (gif0, gif1). lsout4l and lsout4r output a same signal. due to chip layout, lsout4l and lsout4r are arranged on the left and right sides respectively. use either one of them and left the other open. gaon 1 i mpu or gnd gate-all-on signal. gaon = ?1?: gate output signal ?h? gaon = ?0?: gate output signal ?l? output form sout3/4 and lsout3/4. dummy1-12 12 o - test pins. must be disconnected. select interfacing mode with mpu. im1 im0/id mpu interfacing mode pins gnd id serial peripheral interface (spi) sdi/scl vcc * border color setting (de transfer mode) bmode3 im1, im0(id) 2 i gnd or vcc use im0 pin to make a device code id setting. rgb i/f mode: use im1 = gnd. de transfer mode: use im1 = vcc. HD66779 rev.1.00, june.13.2003, page 15 of 70 signals number of pins i/o connected to function cs 1 i mpu chip selection signal for serial peripheral interface (spi). ?low?: select (accessible) ?high?: (inaccessible) when not used, fix to the ?vcc? level. scl 1 i mpu synchronizing clock signal for serial peripheral interface (spi). when not used, fix to the ?vcc? level. sdi 1 i mpu serial data input pin (sdi) for serial peripheral interface (spi). when not used, fix it to the ?vcc? level. ssmd1 1 i mpu or gnd specify the transfer mode. ssmd1 = ?h?: de transfer mode (serial peripheral interface (spi) is not available) ssmd1 = ?l?: rgb i/f mode (serial peripheral interface (spi) is available.) HD66779 rev.1.00, june.13.2003, page 16 of 70 pad arrangement chi p size: 15.00mm x 1.50mm chi p thickness: 550 m ( t yp . ) :w pad coordinate: pad cente r coordinate ori g in: chi p cente r au bum p size: ( 1 ) 63 m x 40 m dummy: no.1 to no.7, no185 to no.191 ( 2 ) 59 m x 92 m input side: no.8 to no.184 ( 3 ) 40 m x 63 m laced lcd output side: no.192 to no.557 :w au bum p p itch: refer to pad coordinate au bum p hei g ht: 15 m ( t yp . ) numbers in the fi g ure refer to numbers in pad coordinate. ali g nment mar k (1) arran g ement: two places aa coordinate ( x, y ) = ( :? 7294.5, -544.5 ) (2-a) coordinate (x, y) = (- 7344.5, -402.6) (2-b) coordinate (x, y) = (7344.5, -402.6) 50 c- 50 c- 20 30 40 30 100 c- 50 30 40 30 50 100 c- n o.7 n o.1 dummy7 dummy6 dummy5 dummy4 dummy3 dummy2 dummy1 @?@?@?@?@?@?@? @? s1 n o.557 @? s2 n o.8 sout1 l @?:w :w:w:w:w:w:w:w@? s3 sout1 l @?:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w:w@? s4 sout2 l @? sout2 l @? sout3 l @? sout3 l @? sout4 l @? sout4 l @? vccdum1 @? eio1 @? lsout1l @? lsout2l @? lsout3l @? lsout4l @? ml @? testg1l @? testg2l @? testg3l @? reset @? im1 @? im0 @? bmode1 @? bmode2 @? bmode3 @? shl @? dpl @? epl @? bp1 @? test4 @? test1 @? lsenl @? lsenr @? chreg @? test5 @? ssmd1 @? testsm2 @? gnddum1 @? testm2 @? testps @? poc @? gaon @? gnddum2 @? vccdum2 @? tests @? cs @? scl @? sdi @? gdndum3 @? pd0 @? pd1 @? pd2 @? pd3 @? pd4 @? pd5 @? pd6 @? pd7 @? pd8 @? pd9 @? pd10 @? pd11 @? pd12 @? pd13 @? pd14 @? pd15 @? pd16 @? pd17 @? enable @? hsync @? vsync @? dotcl k @? gnddum4 @? vcc @? vcc @? vcc @? vcc @? vcc @? vcc @? gnd @? gnd @? gnd @? gnd @? gnd @? gnd @? vgl @? vgl @? vgl @? vgl @? vgl @? vgl @? agnd @? agnd @? agnd @? agnd @? agnd @? HD66779 top view (bump view) laced arrangem ent y x agnd @? ddvdh @? ddvdh @? ddvdh @? ddvdh @? ddvdh @? ddvdh @? vgh @? vgh @? vgh @? vgh @? vgh @? vgh @? vref0p @? vref1p @? vref2p @? vref3p @? vref4p @? vref0n @? vref1n @? vref2n @? vref3n @? vref4n @? vtest @? itest @? comp @? ts0 @? ts1 @? comm @? vcomrc @? vcomrc @? vcomrc @? vcoms @? vcoms @? vcoms @? vcomr @? vcommh @? vcomhc @? vcomhc @? vcomhc @? veq @? veq @? vcomc @? vcomc @? vcomc @? vccdum3 @? clw0 @? clw1 @? sdt0 @? sdt1 @? test6 @? test7 @? test8 @? test9 @? test10 @? test11 @? test12 @? test13 @? test14 @? test15 @? vcomg @? gif0 @? gif1 @? gnddum5 @? reset @? testg3r @? testg2r @? testg1r @? mr @? lsout4r @? lsout3r @? lsout2r @? lsout1r @? eio2 @? vccdum4 @? sout4r @? sout4r @? sout3r @? sout3r @? sout2r @? sout2r @? sout1r @?@? s363 n o.184 sout1r @?@? s364 @? s365 @? s366 n o.192 @?@?@?@?@?@?@? dummy14 dummy13 dummy12 dummy11 dummy10 dummy9 dummy8 no.185 no .191 HD66779 rev.1.00, june.13.2003, page 17 of 70 pad coordinate input, short side n o. p ad name x y n o. p ad name x y 1 dummy1 -7355.9 304.5 101 agnd -31 -594.9 2 dummy2 -7355.9 217.5 102 agnd 54.6 -594.9 3 dummy3 -7355.9 130.5 103 ddvdh 202.2 -594.9 4 dummy4 -7355.9 43.5 104 ddvdh 287.8 -594.9 5 dummy5 -7355.9 -43.5 105 ddvdh 373.4 -594.9 6 dummy6 -7355.9 -130.5 106 ddvdh 459 -594.9 7 dummy7 -7355.9 -217.5 107 ddvdh 544.6 -594.9 8 sout1l -7006.5 -594.9 108 ddvdh 630.2 -594.9 9 sout1l -6920.9 -594.9 109 vgh 741.5 -594.9 10 sout2l -6835.3 -594.9 110 vgh 828.5 -594.9 11 sout2l -6749.7 -594.9 111 vgh 915.5 -594.9 12 sout3l -6664.1 -594.9 112 vgh 1002.5 -594.9 13 sout3l -6578.5 -594.9 113 vgh 1089.5 -594.9 14 sout4l -6492.9 -594.9 114 vgh 1176.5 -594.9 15 sout4l -6407.3 -594.9 115 vref0p 1287.7 -594.9 16 vccdum1 -6278.3 -594.9 116 vref1p 1373.3 -594.9 17 eio1 -6160.6 -594.9 117 vref2p 1458.9 -594.9 18 lsout1l -6101.8 -466.1 118 vref3p 1544.5 -594.9 19 lsout2l -6043 -594.9 119 vref4p 1630.1 -594.9 20 lsout3l -5984.2 -466.1 120 vref0n 1715.7 -594.9 21 lsout4l -5925.4 -594.9 121 vref1n 1801.4 -594.9 22 ml -5866.6 -466.1 122 vref2n 1887 -594.9 23 testg1l -5807.8 -594.9 123 vref3n 1972.6 -594.9 24 testg2l -5749 -466.1 124 vref4n 2058.2 -594.9 25 testg3l -5690.1 -594.9 125 vtest 2143.8 -594.9 26 reset -5631.3 -466.1 126 itest 2229.4 -594.9 27 im1 -5572.5 -594.9 127 comp 2356.2 -594.9 28 im0 -5513.7 -466.1 128 ts0 2441.8 -594.9 29 bmode1 -5454.9 -594.9 129 ts1 2527.4 -594.9 30 bmode2 -5396.1 -466.1 130 comm 2613 -594.9 31 bmode3 -5337.3 -594.9 131 vcomrc 2739.8 -594.9 32 shl -5278.5 -466.1 132 vcomrc 2825.4 -594.9 33 dpl -5219.7 -594.9 133 vcomrc 2911 -594.9 34 epl -5160.8 -466.1 134 vcoms 2996.6 -594.9 35 bp1 -5102 -594.9 135 vcoms 3082.2 -594.9 36 test4 -5043.2 -466.1 136 vcoms 3167.8 -594.9 37 test1 -4984.4 -594.9 137 vcomr 3294.6 -594.9 38 lsenl -4925.6 -466.1 138 vcommh 3380.2 -594.9 39 lsenr -4866.8 -594.9 139 vcomhc 3507 -594.9 40 chreg -4808 -466.1 140 vcomhc 3592.6 -594.9 41 test5 -4749.2 -594.9 141 vcomhc 3678.2 -594.9 42 ssmd1 -4690.3 -466.1 142 veq 3763.8 -594.9 43 testsm2 -4631.5 -594.9 143 veq 3849.5 -594.9 44 gnddum1 -4513.9 -594.9 144 vcomc 4037.2 -594.9 45 testm2 -4396.3 -594.9 145 vcomc 4122.8 -594.9 46 testps -4337.5 -466.1 146 vcomc 4208.4 -594.9 47 poc -4278.7 -594.9 147 vccdum3 4348.8 -594.9 48 gaon -4219.8 -466.1 148 clw0 4466.5 -594.9 49 gnddum2 -4102.2 -594.9 149 clw1 4525.3 -466. 1 50 vccdum2 -3984.6 -594.9 150 sdt0 4584.1 -594.9 51 tests -3867 -594.9 151 sdt1 4642.9 -466.1 52 cs -3808.2 -466.1 152 test6 4701.7 -594.9 53 scl -3749.4 -594.9 153 test7 4760.5 -466.1 54 sdi -3690.5 -466.1 154 test8 4819.3 -594.9 55 gnddum3 -3572.9 -594.9 155 test9 4878.1 -466.1 56 pd0 -3455.3 -594.9 156 test10 4937 -594.9 57 pd1 -3396.5 -466.1 157 test11 4995.8 -466.1 58 pd2 -3337.7 -594.9 158 test12 5054.6 -594.9 59 pd3 -3278.9 -466.1 159 test13 5113.4 -466.1 60 pd4 -3220 -594.9 160 test14 5172.2 -594.9 61 pd5 -3161.2 -466.1 161 test15 5231 -466.1 62 pd6 -3102.4 -594.9 162 vcomg 5289.8 -594.9 63 pd7 -3043.6 -466.1 163 gif0 5348.6 -466.1 64 pd8 -2984.8 -594.9 164 gif1 5407.5 -594.9 65 pd9 -2926 -466.1 165 gnddum5 5525.1 -594.9 66 pd10 -2867.2 -594.9 166 reset 5642.7 -594.9 67 pd11 -2808.4 -466.1 167 testg3r 5701.5 -466.1 68 pd12 -2749.5 -594.9 168 testg2r 5760.3 -594.9 69 pd13 -2690.7 -466.1 169 testg1r 5819.1 -466.1 70 pd14 -2631.9 -594.9 170 mr 5878 -594.9 71 pd15 -2573.1 -466.1 171 lsout4r 5936.8 -466.1 72 pd16 -2514.3 -594.9 172 lsout3r 5995.6 -594.9 73 pd17 -2455.5 -466.1 173 lsout2r 6054.4 -466.1 74 enable -2396.7 -594.9 174 lsout1r 6113.2 -594.9 75 hsync -2337.9 -466.1 175 eio2 6172 -466.1 76 vsync -2279.1 -594.9 176 vccdum4 6289.6 -594.9 77 dotcl k -2220.2 -466.1 177 sout4r 6407.3 -594.9 78 gnddum4 -2102.6 -594.9 178 sout4r 6492.9 -594.9 79 vcc -2001.2 -594.9 179 sout3r 6578.5 -594.9 80 vcc -1914.2 -594.9 180 sout3r 6664.1 -594.9 81 vcc -1827.2 -594.9 181 sout2r 6749.7 -594.9 82 vcc -1740.2 -594.9 182 sout2r 6835.3 -594.9 83 vcc -1653.2 -594.9 183 sout1r 6920.9 -594.9 84 vcc -1566.2 -594.9 184 sout1r 7006.5 -594.9 85 gnd -1452 -594.9 185 dummy14 7355.9 -217.5 86 gnd -1366.4 -594.9 186 dummy13 7355.9 -130.5 87 gnd -1280.8 -594.9 187 dummy12 7355.9 -43.5 88 gnd -1195.2 -594.9 188 dummy11 7355.9 43.5 89 gnd -1109.6 -594.9 189 dummy10 7355.9 130.5 90 gnd -1024 -594.9 190 dummy9 7355.9 217.5 91 vgl -912.7 -594.9 191 dummy8 7355.9 304.5 92 vgl -827.1 -594.9 93 vgl -741.5 -594.9 94 vgl -655.9 -594.9 95 vgl -570.3 -594.9 96 vgl -484.7 -594.9 97 agnd -373.4 -594.9 98 agnd -287.8 -594.9 99 agnd -202.2 -594.9 100 agnd -116.6 -594. 9 HD66779 rev.1.00, june.13.2003, page 18 of 70 laced output arrangement no. p ad name x y no. p ad name x y 192 s366 7300.5 609.1 258 s300 4660.3 609.1 193 s365 7260.5 505.5 259 s299 4620.3 505.5 194 s364 7220.5 609.1 260 s298 4580.3 609.1 195 s363 7180.5 505.5 261 s297 4540.3 505.5 196 s362 7140.5 609.1 262 s296 4500.3 609.1 197 s361 7100.5 505.5 263 s295 4460.3 505.5 198 s360 7060.5 609.1 264 s294 4420.3 609.1 199 s359 7020.5 505.5 265 s293 4380.3 505.5 200 s358 6980.5 609.1 266 s292 4340.3 609.1 201 s357 6940.5 505.5 267 s291 4300.3 505.5 202 s356 6900.4 609.1 268 s290 4260.3 609.1 203 s355 6860.4 505.5 269 s289 4220.3 505.5 204 s354 6820.4 609.1 270 s288 4180.3 609.1 205 s353 6780.4 505.5 271 s287 4140.3 505.5 206 s352 6740.4 609.1 272 s286 4100.3 609.1 207 s351 6700.4 505.5 273 s285 4060.3 505.5 208 s350 6660.4 609.1 274 s284 4020.3 609.1 209 s349 6620.4 505.5 275 s283 3980.3 505.5 210 s348 6580.4 609.1 276 s282 3940.3 609.1 211 s347 6540.4 505.5 277 s281 3900.3 505.5 212 s346 6500.4 609.1 278 s280 3860.3 609.1 213 s345 6460.4 505.5 279 s279 3820.2 505.5 214 s344 6420.4 609.1 280 s278 3780.2 609.1 215 s343 6380.4 505.5 281 s277 3740.2 505.5 216 s342 6340.4 609.1 282 s276 3700.2 609.1 217 s341 6300.4 505.5 283 s275 3660.2 505.5 218 s340 6260.4 609.1 284 s274 3620.2 609.1 219 s339 6220.4 505.5 285 s273 3580.2 505.5 220 s338 6180.4 609.1 286 s272 3540.2 609.1 221 s337 6140.4 505.5 287 s271 3500.2 505.5 222 s336 6100.4 609.1 288 s270 3460.2 609.1 223 s335 6060.4 505.5 289 s269 3420.2 505.5 224 s334 6020.4 609.1 290 s268 3380.2 609.1 225 s333 5980.4 505.5 291 s267 3340.2 505.5 226 s332 5940.4 609.1 292 s266 3300.2 609.1 227 s331 5900.4 505.5 293 s265 3260.2 505.5 228 s330 5860.4 609.1 294 s264 3220.2 609.1 229 s329 5820.4 505.5 295 s263 3180.2 505.5 230 s328 5780.4 609.1 296 s262 3140.2 609.1 231 s327 5740.4 505.5 297 s261 3100.2 505.5 232 s326 5700.4 609.1 298 s260 3060.2 609.1 233 s325 5660.4 505.5 299 s259 3020.2 505.5 234 s324 5620.4 609.1 300 s258 2980.2 609.1 235 s323 5580.4 505.5 301 s257 2940.2 505.5 236 s322 5540.4 609.1 302 s256 2900.2 609.1 237 s321 5500.4 505.5 303 s255 2860.2 505.5 238 s320 5460.4 609.1 304 s254 2820.2 609.1 239 s319 5420.4 505.5 305 s253 2780.2 505.5 240 s318 5380.4 609.1 306 s252 2740.2 609 .1 241 s317 5340.3 505.5 307 s251 2700.2 505.5 242 s316 5300.3 609.1 308 s250 2660.2 609.1 243 s315 5260.3 505.5 309 s249 2620.2 505.5 244 s314 5220.3 609.1 310 s248 2580.2 609.1 245 s313 5180.3 505.5 311 s247 2540.2 505.5 246 s312 5140.3 609.1 312 s246 2500.2 609.1 247 s311 5100.3 505.5 313 s245 2460.2 505.5 248 s310 5060.3 609.1 314 s244 2420.2 609.1 249 s309 5020.3 505.5 315 s243 2380.2 505.5 250 s308 4980.3 609.1 316 s242 2340.2 609.1 251 s307 4940.3 505.5 317 s241 2300.2 505.5 252 s306 4900.3 609.1 318 s240 2260.1 609.1 253 s305 4860.3 505.5 319 s239 2220.1 505.5 254 s304 4820.3 609.1 320 s238 2180.1 609.1 255 s303 4780.3 505.5 321 s237 2140.1 505.5 256 s302 4740.3 609.1 322 s236 2100.1 609.1 257 s301 4700.3 505.5 323 s235 2060.1 505.5 324 s234 2020.1 609.1 325 s233 1980.1 505.5 326 s232 1940.1 609.1 327 s231 1900.1 505.5 328 s230 1860.1 609.1 329 s229 1820.1 505.5 330 s228 1780.1 609.1 331 s227 1740.1 505.5 332 s226 1700.1 609.1 333 s225 1660.1 505.5 334 s224 1620.1 609.1 335 s223 1580.1 505.5 336 s222 1540.1 609.1 337 s221 1500.1 505.5 338 s220 1460.1 609.1 339 s219 1420.1 505.5 340 s218 1380.1 609.1 341 s217 1340.1 505.5 342 s216 1300.1 609.1 343 s215 1260.1 505.5 344 s214 1220.1 609.1 345 s213 1180.1 505.5 346 s212 1140.1 609.1 347 s211 1100.1 505.5 348 s210 1060.1 609.1 349 s209 1020.1 505.5 350 s208 980.1 609.1 351 s207 940.1 505.5 352 s206 900.1 609.1 353 s205 860.1 505.5 354 s204 820.1 609.1 355 s203 780.1 505.5 356 s202 740 609.1 357 s201 700 505. 5 no. p ad name x y no. p ad name x y 358 s200 660 609.1 458 s100 -3340.2 609.1 359 s199 620 505.5 459 s99 -3380.2 505.5 360 s198 580 609.1 460 s98 -3420.2 609.1 361 s197 540 505.5 461 s97 -3460.2 505.5 362 s196 500 609.1 462 s96 -3500.2 609.1 363 s195 460 505.5 463 s95 -3540.2 505.5 364 s194 420 609.1 464 s94 -3580.2 609.1 365 s193 380 505.5 465 s93 -3620.2 505.5 366 s192 340 609.1 466 s92 -3660.2 609.1 367 s191 300 505.5 467 s91 -3700.2 505.5 368 s190 260 609.1 468 s90 -3740.2 609.1 369 s189 220 505.5 469 s89 -3780.2 505.5 370 s188 180 609.1 470 s88 -3820.2 609.1 371 s187 140 505.5 471 s87 -3860.3 505.5 372 s186 100 609.1 472 s86 -3900.3 609.1 373 s185 60 505.5 473 s85 -3940.3 505.5 374 s184 20 609.1 474 s84 -3980.3 609.1 375 s183 -20 505.5 475 s83 -4020.3 505.5 376 s182 -60 609.1 476 s82 -4060.3 609.1 377 s181 -100 505.5 477 s81 -4100.3 505.5 378 s180 -140 609.1 478 s80 -4140.3 609.1 379 s179 -180 505.5 479 s79 -4180.3 505.5 380 s178 -220 609.1 480 s78 -4220.3 609.1 381 s177 -260 505.5 481 s77 -4260.3 505.5 382 s176 -300 609.1 482 s76 -4300.3 609.1 383 s175 -340 505.5 483 s75 -4340.3 505.5 384 s174 -380 609.1 484 s74 -4380.3 609.1 385 s173 -420 505.5 485 s73 -4420.3 505.5 386 s172 -460 609.1 486 s72 -4460.3 609.1 387 s171 -500 505.5 487 s71 -4500.3 505.5 388 s170 -540 609.1 488 s70 -4540.3 609.1 389 s169 -580 505.5 489 s69 -4580.3 505.5 390 s168 -620 609.1 490 s68 -4620.3 609.1 391 s167 -660 505.5 491 s67 -4660.3 505.5 392 s166 -700 609.1 492 s66 -4700.3 609.1 393 s165 -740 505.5 493 s65 -4740.3 505.5 394 s164 -780.1 609.1 494 s64 -4780.3 609.1 395 s163 -820.1 505.5 495 s63 -4820.3 505.5 396 s162 -860.1 609.1 496 s62 -4860.3 609.1 397 s161 -900.1 505.5 497 s61 -4900.3 505.5 398 s160 -940.1 609.1 498 s60 -4940.3 609.1 399 s159 -980.1 505.5 499 s59 -4980.3 505.5 400 s158 -1020.1 609.1 500 s58 -5020.3 609.1 401 s157 -1060.1 505.5 501 s57 -5060.3 505.5 402 s156 -1100.1 609.1 502 s56 -5100.3 609.1 403 s155 -1140.1 505.5 503 s55 -5140.3 505.5 404 s154 -1180.1 609.1 504 s54 -5180.3 609.1 405 s153 -1220.1 505.5 505 s53 -5220.3 505.5 406 s152 -1260.1 609.1 506 s52 -5260.3 609. 1 407 s151 -1300.1 505.5 507 s51 -5300.3 505.5 408 s150 -1340.1 609.1 508 s50 -5340.3 609.1 409 s149 -1380.1 505.5 509 s49 -5380.3 505.5 410 s148 -1420.1 609.1 510 s48 -5420.4 609.1 411 s147 -1460.1 505.5 511 s47 -5460.4 505.5 412 s146 -1500.1 609.1 512 s46 -5500.4 609.1 413 s145 -1540.1 505.5 513 s45 -5540.4 505.5 414 s144 -1580.1 609.1 514 s44 -5580.4 609.1 415 s143 -1620.1 505.5 515 s43 -5620.4 505.5 416 s142 -1660.1 609.1 516 s42 -5660.4 609.1 417 s141 -1700.1 505.5 517 s41 -5700.4 505.5 418 s140 -1740.1 609.1 518 s40 -5740.4 609.1 419 s139 -1780.1 505.5 519 s39 -5780.4 505.5 420 s138 -1820.1 609.1 520 s38 -5820.4 609.1 421 s137 -1860.1 505.5 521 s37 -5860.4 505.5 422 s136 -1900.1 609.1 522 s36 -5900.4 609.1 423 s135 -1940.1 505.5 523 s35 -5940.4 505.5 424 s134 -1980.1 609.1 524 s34 -5980.4 609.1 425 s133 -2020.1 505.5 525 s33 -6020.4 505.5 426 s132 -2060.1 609.1 526 s32 -6060.4 609.1 427 s131 -2100.1 505.5 527 s31 -6100.4 505.5 428 s130 -2140.1 609.1 528 s30 -6140.4 609.1 429 s129 -2180.1 505.5 529 s29 -6180.4 505.5 430 s128 -2220.1 609.1 530 s28 -6220.4 609.1 431 s127 -2260.1 505.5 531 s27 -6260.4 505.5 432 s126 -2300.1 609.1 532 s26 -6300.4 609.1 433 s125 -2340.2 505.5 533 s25 -6340.4 505.5 434 s124 -2380.2 609.1 534 s24 -6380.4 609.1 435 s123 -2420.2 505.5 535 s23 -6420.4 505.5 436 s122 -2460.2 609.1 536 s22 -6460.4 609.1 437 s121 -2500.2 505.5 537 s21 -6500.4 505.5 438 s120 -2540.2 609.1 538 s20 -6540.4 609.1 439 s119 -2580.2 505.5 539 s19 -6580.4 505.5 440 s118 -2620.2 609.1 540 s18 -6620.4 609.1 441 s117 -2660.2 505.5 541 s17 -6660.4 505.5 442 s116 -2700.2 609.1 542 s16 -6700.4 609.1 443 s115 -2740.2 505.5 543 s15 -6740.4 505.5 444 s114 -2780.2 609.1 544 s14 -6780.4 609.1 445 s113 -2820.2 505.5 545 s13 -6820.4 505.5 446 s112 -2860.2 609.1 546 s12 -6860.4 609.1 447 s111 -2900.2 505.5 547 s11 -6900.4 505.5 448 s110 -2940.2 609.1 548 s10 -6940.5 609.1 449 s109 -2980.2 505.5 549 s9 -6980.5 505.5 450 s108 -3020.2 609.1 550 s8 -7020.5 609.1 451 s107 -3060.2 505.5 551 s7 -7060.5 505.5 452 s106 -3100.2 609.1 552 s6 -7100.5 609.1 453 s105 -3140.2 505.5 553 s5 -7140.5 505.5 454 s104 -3180.2 609.1 554 s4 -7180.5 609.1 455 s103 -3220.2 505.5 555 s3 -7220.5 505.5 456 s102 -3260.2 609.1 556 s2 -7260.5 609.1 457 s101 -3300.2 505.5 557 s1 -7300.5 505. 5 HD66779 rev.1.00, june.13.2003, page 19 of 70 instruction the HD66779 incorporates interface with microcomputer, which enables instruction setting to realize high- quality display and low power consumption. with regard to settings and timing of interface, see ?serial peripheral interface (spi) function?. the instruction setting can not be made in de transfer mode. index: ir ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 instruction 0 0 0 0 0 0 0 0 0 0 0 0 0 id2 id1 id0 initialized value - - - - - - - - - - - - - - - - specifies an index registor to be accessed. do not try to access to the register to which instruction is not assigned. power save, color control: r01h ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 instruction 0 0 0 0 0 0 poc 1 0 0 0 0 0 0 0 0 initialized value - - - - - - 0 - - - - - - - - - poc: power control function. poc = ?1?: normal operation mode. both input/output interfaces are operable. poc = ?0?: power control mode. white display is shown for the entire screen. note 1) when ?chreg? = ?h?, ?poc? of instruction register r01 become valid. note 2) see ?power control function? for details. note 3) the setting becomes effective in the next vsync assert timing. HD66779 rev.1.00, june.13.2003, page 20 of 70 border color control (1): r02h ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 instruction 0 0 0 0 0 0 0 0 0 0 bco l17 bco l16 bco l15 bco l14 bco l13 bco l12 initialized value - - - - - - - - - - 1 1 1 1 1 1 border color control (2): r03h ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 instruction 0 0 bco l11 bco l10 bco l9 bco l8 bco l7 bco l6 0 0 bco l5 bco l4 bco l3 bco l2 bco l1 bco l0 initialized value - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 bcol17-0: set value for the border color. the assignment of the value to each register is as follows. bcol17-12: s (3n+1) bcol11-6: s (3n+2) bcol5-0: s (3n+3) note 1) the border pin assignment changes according to the setting for the border color control. bmode2 = ?h?: n = 0 to 1 bmode2 = ?l?: n = 120 to 121 note 2) vertical border area is made by 2 raster-rows each at the top and bottom of the screen. note 3) horizontal border area is made by 6 channels (two rgbs) each at the left and right sides of the screen. note 4) the settings for the border control must be made during non-display period. note 5) the setting becomes effictive from the next vsync assert timing. note 6) the setting is invalid while the border function is not used. note 7) the border color control functon is valid only in rgbi/f mode. the set values are assigned as follows. bc 17 bc 16 bc 15 bc 14 bc 13 bc 12 bc 11 bc 10 bc 9 bc 8 bc 7 bc 6 bc 5 bc 4 bc 3 bc 2 bc 1 bc 0 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 s (3n+1) s (3n+2) s (3n+3) border value rgb assignment exam p le output pin s * n = 0 to 121 HD66779 rev.1.00, june.13.2003, page 21 of 70 lcd driving waveform control, source output control: r04h ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 instruction 0 0 0 0 0 0 nw1 nw0 0 0 0 0 rb3 rb2 rb1 rb0 initialized value - - - - - - 0 1 - - - - 1 0 0 0 nw2-0: selects ac timing. nw1 nw0 alternating timing 0 0 frame inversion 0 1 inversion by line 1 0 inversion by 2 lines 1 1 setting disabled note 1) for details, see ?lcd ac drive?. note 2) the setting becomes effective from the next vsync assert timing. bp3-0: set the blank period (back porch) in the following figure. bp3-0 set the number of raster-rows for the back porch. the number of raster-rows for the back porch should be: 14 raster-rows the number of raster-rows for the back porch ? the number of raster-rows for the border 2 raster-rows note 1) when ?chreg? = ?h?, instruction registers ?bp3?, ?bp2?, ?bp1?, ?bp0? become valid. when ?chreg? = ?l?, ?bp? pin function becomes valid. (?bp?= 0: back porch 4 lines, ?bp?=1: back porch 8 lines) note 2) a front porch lasts from the end of the display pixel transfer to the next vsync assert. note 3) the setting becomes effective from the next assert timing. display data back porch front porch vsync HD66779 rev.1.00, june.13.2003, page 22 of 70 bp3 bp2 bp1 bp0 back porch line 0 0 0 0 setting disabled 0 0 0 1 setting disabled 0 0 1 0 two lines 0 0 1 1 three lines 0 1 0 0 four lines 1 1 0 0 12 lines 1 1 0 1 13 lines 1 1 1 0 14 lines 1 1 1 1 setting disabled gate non overlap control, border color control: r05h ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 instruction 0 0 0 dte 0 0 no1 no0 0 0 0 0 0 0 0 gao n initialized value - - - 1 - - 0 0 - - - - - - - 0 dte : output gate off signal. ?dte? = ?0?: fix to gnd. ?dte? = ?1?: output gate off signal. the setting becomes effective from the next vsync assert timing. no1-0: set the non-overlap period of gate off signal. amount of non-overlap no1 no0 delay time 5mhz (e.g.) 0 0 0 s 0 clock 0 1 4.0 s 20 clocks 1 0 6.0 s 30 clocks 1 1 8.0 s 40 clocks note) the delay time changes according to the dotclk frequency. HD66779 rev.1.00, june.13.2003, page 23 of 70 1h perio d 1h perio d non-overlap period sout2 (line cycle clock) sout3 sout4 (gate-off signal) non-overlap perio d (line cycle clock) note) when the setting is made with pins, the non-overla p amount of gate off signal equals to that set with clw1-0. gaon: output gate-all-on signal. gaon = ?0?: gate output signal l/sout4 = ?0? gaon = ?1?: gate ouput signal l/sout4 = ?1? note 1) when ?chreg? = ?h?, ?gaon? of instruction register r05 becomes valid. note 2) with regard to the selection of output pin, see ?lcd display signal control?. note 3) the setting becomes effective from the next vsync assert timing. display signal select control, flame control 1: r06h ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 instruction 0 0 dsc 1 dsc 0 0 0 gif1 gif0 fhn 0 fth 1 fth 0 0 0 fwh 1 fwh 0 initialized value - - 0 1 - - 0 0 1 - 1 0 - - 1 1 dsc1-0: controls start/halt of lcd signals. dsc1 dsc0 selective signal for lcd display 0 0 halt lcd display signal 0 1 sout1/2/3/4 1 0 lsout 1/2/3/4 1 1 l/sout1/2/3/4 note 1) sout1/2/3/4 is a level shifter output (voltage between vgh and vgl), and lsout1/2/3/4 is a logic output (voltage between vcc and gnd). note 2) the setting becoms effectiv e from the next vsync assert timing. HD66779 rev.1.00, june.13.2003, page 24 of 70 gif1-0: select the function of lcd display signal. gif1 gif0 l/sout2 l/sout3 l/sout4 0 0 line frequency clock 1 line frequency clock 2 disconnect pins 0 1 line frequency clock 1 line frequency clock 2 gete off signal 1 0 line frequency clock 1 line frequency clock 2 gate all on 1 1 line frequency clock 3 gate all on gate off signal note 1) when ?chreg? = ?h?, ?gif1? and ?gif0? of instruction registers r06 become effective. note 2) the setting becoms effectiv e from the next vsync assert timing. note 3) when ?gif1-0? = 11, ?fhn? = ?0?(1h assert). 1 frame 2h 1h display period blank period blank period vsync dotclk gif1-0 = 00 sout1 (frame signal) sout2 sout3 (lin cycle clock 2) sout4 (gate-off signal) sout4 (gate all on signal) gif1-0 = 01 gif1-0 = 10 blank period blank p eriod display period 1h gif1-0 = 11 sout1 ( frame si g nal ) sout2 (line cycle clock 3) sout3 (gate all on signal) sout4 (gate-off signal) (lin cycle clock 1) gif1-0: timing chart HD66779 rev.1.00, june.13.2003, page 25 of 70 fhn: set the assert period of sout1 signal (frame timing signal) during horizontal period. fhn = ?0?: the assert available for 1h period. fhn = ?1?: the assert available for 2h period. the setting becomes effective from the next vsync assert timing. the assert period is 2h in de transfer mode (1h, when gif1-0 = ?11?). fti1-0: set the assert timing of sout1 signal (frame timing signal) during horizontal period. assert timing fti1 fti0 delay time 5mhz (e.g.) 0 0 0 s 0 clock 0 1 1.5 s 7.5 clocks 1 0 3.5 s 17.5 clocks 1 1 7.5 s 37.5 clocks note ) the delay time cahges according to the dotclk frequency. the setting becomes effective from the next vsync assert timing. fwi1-0: set the pulse width of sout1 signal (frame timing signal) during ?high?. ?high? period fwi1 fwi0 delay time 5mhz (ex.) 0 0 2 s 10 clocks 0 1 8 s 40 clocks 1 0 16 s 80 clocks 1 1 until the end of 1h period ? the setting becomes effective from the next vsync assert timing. HD66779 rev.1.00, june.13.2003, page 26 of 70 instruction list bit 0 id0 0 bcol12 1 bcol0 1 *bp0 0 *gaon 0 fwi0 1 bit 1 id1 0 bcol13 1 bcol1 1 *bp1 0 0 fwi1 1 bit 2 id2 0 bcol14 1 bcol2 1 *bp2 0 0 0 bit 3 0 0 bcol15 1 bcol3 1 *bp3 1 0 0 bit 4 0 0 bcol16 1 bcol4 1 0 0 fti0 0 bit 5 0 0 bcol17 1 bcol5 1 0 0 fti1 1 bit 6 0 0 0 0 0 0 0 bit 7 0 0 0 0 0 0 fhn 1 bit 8 0 1 0 bcol6 1 nw0 1 no0 1 *gif0 0 bit 9 0 *poc 0 0 bcol7 1 nw1 0 no1 0 *gif1 0 bit 10 0 0 0 bcol8 1 0 0 0 bit 11 0 0 0 bcol9 1 0 0 0 bit 12 0 0 0 bcol10 1 0 dte 1 dsc0 1 bit 13 0 0 0 bcol11 1 0 0 dsc1 0 bit 14 0 0 0 0 0 0 0 bit 15 0 0 0 0 0 0 0 index power control color control border color control (1) border color control (2) lcd drive ac control, display control gate output non-overlap control, all gate on control signal select control for lcd display, flm contro l r01h r02h r03h r04h r05h r06h note 1) the initialized value is shown at the bottom of each instruction bit cell. note 2) do not try to access to the regist er where instruction setting is disabled. note 3) the setting in the instruction bit with ?*? conf licts with the pin setting. when the pin ?chreg? is set to ?h?, the setting of the instruction bi t takes precedence over the pin setting. note 4) in the de transfer mode, the setting of the bi t without ?*? is not changeable and initialized value is retained. HD66779 rev.1.00, june.13.2003, page 27 of 70 reset function the HD66779 is internally initialized with the input of reset. during reset period, the intenal state of the HD66779 is busy and no external access is accepted. with the reset input to the HD66779, the settings for the gate-driver/power supply ic are not automatically initialized and separate resetting is required for the gate-driver/power supply ic. the reset input period must be held for 1 ms at least. do not transfer initialized instruction sets or data during the power-on reset when power is turned on. 1. initial state of instruction set : see description for each instruction 2. initial level of output pin : lcd display output: sout1-4r/l output ?vgl? level. lsout1-4r/l output ?gnd?level. ac drive amplitude signal vcoms output ?gnd? level. HD66779 rev.1.00, june.13.2003, page 28 of 70 lcd signal output timing control function adjust output timing of lcd display signal with external pins. clw0/1: set output position of line cycle clock for display. delay amount clw1 clw0 delay time 5mhz (e.g.) l l 0 s 0 clock l h 2.0 s 10 clocks h l 4.0 s 20 clocks h h 6.0 s 30 clocks note) the delay time changes according to the dotclk frequency. sdt0/1: set output position of source output. delay amount sdt1 sdt0 delay time 5mhz (e.g.) l l 2 s 10 clocks l h 3.0 s 15 clocks h l 4.0 s 20 clocks h h 5.0 s 25 clocks note) the delay time changes according to the dotclk frequency. sdt clw clw sout1 source output (s1 to s366) ex.) gate selecting signal g1 output timing sout2 sout3 g2 g3 1 line 2 line sdt 3 line 4 line 5 line HD66779 rev.1.00, june.13.2003, page 29 of 70 lcd signal timing control function the timing chart of control signals is illustrated as follows. display line sout1 (frame cycle) sout3 s1 to 492 (source output) vcoms (vcom amplitude) sout4 (gate off) reference point reference point reference point referenc e point 1h period 1h period 1h period second line third line first line fhn fwi fti clw sdt sdt sdt no no no sout2 (line cycle clock) clw c lw dotclk (dpl = 0 ) tc tc tc tc tc tc tc tc reference signal rgbi/f mode hsync reference signal de transfer mode enable (de) (line cycle clock) note 1) there are some constraints when the pin setting is effective. l/sout1 (frame) signal is fhn = ?1? (2h assert) when fti1-0 = ?10? (de transfer mo de: fti1-0 = ?00?), fwi1-0 = ?11?. the non-overlap amount of l/sout4 (gate-of f signal) equals to that set by clw1-0. note 2) there are some constraints when gif1-0 = ?11?. fhn = ?0? (1h assert) irrespective of the pin setting and spi setting (fhn = ?1?). when the pin setting is effective, fti1-0 = ?00?, fwi1-0 = ?11?. HD66779 rev.1.00, june.13.2003, page 30 of 70 power control function power control function (poc) when poc = ?l?, a white display is shown. note 1) the panel display signal (sout*) is output normally. note 2) the set value of poc changes with vsync and the source output becomes effective from the next timing. power supply off sequence (example of usage) power supply vsync hsync enable pd17-0 poc HD66779 s1-sxx vcoms sout1 data valid pocw>=1 frame power control ponhw>=1 frame inactive white power supply vsync hsync enable pd17-0 poc HD66779 s1-sxx vcoms sout1 reset pocw>=1 frame ponsw>=1 frame inactive power control data valid white power supply on sequence (example of usage) ponsw: the period from power supply on to the start of h/v synchronizing signal assert pocw: power on control period ponsw: the period from the end of h/v synchronizing signal to power supply off pocw: power on control period HD66779 rev.1.00, june.13.2003, page 31 of 70 poc / vcomg / lsenr/l output control the relationship among these signals is as follows. source output (sn) and vcom output (vcoms) control by poc input output poc operation mode source output (sn) vcom output 0 power control mode white vcoms 1 normal operation mode input data or border data vcoms panel display signal (sout*/lsout*) control by lsenl/lsenr output input vgh-vgl vcc-gnd lsenl lsenr sout1/2/3/4l sout1/2/3/4r lsout1/2/3/4l lsout1/2/3/4r 0 0 vgl vgl 0 1 vgl vgh ? vgl 1 0 vgh ? vgl vgl 1 1 vgh ? vgl vgh ? vgl vcc ? gnd vcc - gnd vcom (vcoms) control by vcomg input output vcomg vcoms 0 gnd 1 vcoms HD66779 rev.1.00, june.13.2003, page 32 of 70 interface rgb interface timing 1 (366ch x 2 / with border) the timing chart of rgb interface signal is as follows. the value for the border is the one received through spi. 1 frame back porch period (bp) front porch period (>=4h) vsync hsync dotclk enable pd17- 0 dis p la y are a vsync hsync enable vlw >=1h 1h 3clk<= hl w <= 5clk ei02 (mas ter) hbp>= 26 clk master slave hfp>= 6 cl k 240 clk 1 2 dotcl k pd17-0 1 2 119 120 121 122 239 240 bd = 2clk bd = 2clk bd bd bd bd border are a border area ( border ) vlw: vsync ?low? period hlw: hsync ? low? period hbp: horizontal period back porch hfp: horizontal period front porch bd: border area HD66779 rev.1.00, june.13.2003, page 33 of 70 rgb interface timing 2 (360ch x 2 / without border) the timing chart of signals in rgb interface is as follows. 1 frame back porch period (bp) front porch period (>=4h) vsync hsync dotclk enable pd17- 0 dis p la y are a vsync hsync dotclk enable vlw >=1h 1h 3clk<= hlw < 5cl k ei02 (mas ter) hbp>= 26 clk master slave hfp>= 6 clk 240 clk 1 2 pd17-0 1 2 119 120 121 122 239 240 vlw: vsync ?low? period hlw: hsync ? low? period hbp: horizontal period back porch hfp: horizontal period front porch HD66779 rev.1.00, june.13.2003, page 34 of 70 lcd panel interface timing 1 (366ch x 2 / with border) the timing chart of rgb interface signal is as follows. the value for the border is the one received through spi. 1 frame back porch period (bp) vsync hsync dotclk enable pd17- 0 back porch period (bp) front porch period ( >=4h) >=1h 1h 318 319 320 2h 2h 1h clw1 -0 clw1 -0 320 bd bd 157 158 159 160 161 bd bd 1 sout1 sout2 sout3 g1 g2 g324 s1-366x2 vcom (m ) sdt1-0 sdt1-0 12 12 34 12 bd bd note) see ?lcd signal timing control func tion? for details of setting the timing. HD66779 rev.1.00, june.13.2003, page 35 of 70 lcd panel interface timing 2 (366ch x 2 / without border) the timing chart of rgb interface signal and lcd panel signal is as follows. 1 frame back porch period (bp) vsync hsync dotclk enable pd17- 0 back porch period (bp) front porch period ( >=4h) >=1h 1h 316 317 318 2h 2h 1h clw1 -0 clw1 -0 316 317 318 157 158 159 160 161 1 sout1 sout2 sout3 g1 g2 g320 s1-360x2 vcom (m ) sdt1-0 sdt1-0 1 1234 319 320 5 12 34 319 320 23 back porch period ( bp) note) see ?lcd signal timing control func tion? for details of setting the timing. HD66779 rev.1.00, june.13.2003, page 36 of 70 de transfer mode 1 (366ch x 2 / with border) the timing chart of de transfer mode signal is as follows. the border color in de transfer mode is either black or white to be switchted with bmode3 pin. 1 frame (more than or equal to 327h) dotclk (mclk) enable (de) pd17- 0 blank period (more than or equal to 7h) display period 320h 254clk<=1h<=479clk 240clk 14clk<=horizontal blank p eriod <= 239cl k 12 119 120 121 239 1 dotclk (mclk) enable (de) pd17- 0 master slave 240 ei02 (master ) bd bd bd bd bd bd HD66779 rev.1.00, june.13.2003, page 37 of 70 de transfer mode 2 (366ch x 2 / without border) the timing chart of de transfer mode signal is as follows. 1 frame (more than or equal to 327h) dotclk (mclk) enable (de) pd17- 0 blank period (more than or equal to 7h) display period 320h 254clk<=1h<=479clk 240clk 14clk<=horizontal blank p eriod <= 239cl k 12 119 120 121 239 1 dotclk (mclk) enable (de) pd17- 0 master slave 240 ei02 (master ) HD66779 rev.1.00, june.13.2003, page 38 of 70 lcd panel interface timing while de transfer mode 1 (with border) the relationship between the de transfer mode signal and the lcd panel signal is as follows. note 1) the border color control while using de transfer mode is on the 6 channels each at left and right side. note 2) the border color in de transfer mode is only black and white to be switched with bmode3 pin. dotclk (mclk) enable (de) pd17- 0 2h clw1 -0 clw1 -0 158 159 160 1 sout1 sout2 sout3 g1 g2 g320 s1-366 x 2 vcom (m ) sdt1-0 sdt1-0 317 318 319 320 1 12 34 23 display period 320h blank period (more than or equal to 7h) 123 45 2h 318 319 32 0 1 frame (more than or equal to 327h) note) see ?lcd signal timing control func tion? for details of setting the timing. HD66779 rev.1.00, june.13.2003, page 39 of 70 lcd panel interface timing while de transfer mode 2 (without border) the relationship between the de transfer mode signal and the lcd panel signal is as follows. 1 frame (more than or equal to 327h) dotclk (mclk) enable (de) pd17- 0 2h clw1 -0 clw1 -0 158 159 160 1 sout1 sout2 sout3 g1 g2 g320 s1-360 x 2 vcom (m ) sdt1-0 sdt1-0 317 318 319 320 1 12 34 23 display period 320h blank period (more than or equal to 7h) 1234 5 2h 318 319 32 0 note) see ?lcd signal timing control func tion? for details of setting the timing. HD66779 rev.1.00, june.13.2003, page 40 of 70 lcd panel interface timing while de transfer mode 3 the relationship between the de transfer mode signal, gate driver outputs and the lcd panel signal is as follows. 1 frame (more than or equal to 327h) dotclk (mclk) enable (de) pd17- 0 2h 158 159 160 1 lsout1 lsout2 lsout4 g1 g2 g320 s1-360 x 2 vcom (m ) sdt1-0 sdt1-0 317 318 319 320 1 12 34 23 display period 320h blank period (more than or equal to 7h) 1234 5 318 319 32 0 1h clw1-0 note) see ?lcd signal timing control func tion? for details of setting the timing. HD66779 rev.1.00, june.13.2003, page 41 of 70 serial peripheral interface (spi) function (only available with rgb i/f) serial peripheral interface (spi) transfer is made by setting im1/ pin to the gnd level. the interfacing is executed through chip select line (cs*), serial transfer clock line (scl), and serial input data (sdi). the HD66779 initiates serial data transfer by recognizing the falling edge of cs* input as a start and then start the transfer of the start byte. the condition for the end of data transfer is that the HD66779 recognizes the rising edge of cs* input as an end of transfer. the HD66779 is selected when the 6-bit chip address in the start byte from the transmission side and the 6- bit device identification code assigned to the HD66779 are compared and matches with each other. the HD66779, when selected, receives data from the subsequent data string. the least significant bit of the identification code can be specified with id pin. the upper five bits of the device id code must be 01110. the 7 th bit of the start byte is assigned to the selection of HD66779?s register (rs) and when this bit is set to 0, index register write is executed and when this bit is set to 1, instruction write is executed. accordingly, two chip addresses must be assigned to one HD66779. after receiving the start byte, the HD66779 receives and transfers data by byte. the transfer data format is msb first. the instruction of the HD66779 comprise 16 bits. the instruction is executed internally after 2- byte (d15-0) transfer with msb first. start byte format example of transfer bit s 1 2 3 4 5 6 7 8 device id code start byte format start 0 1 1 1 0 id rs 0 note) id bit is selected with im0/id pins. rs bit function rs function 0 set index register 1 instruction write HD66779 rev.1.00, june.13.2003, page 42 of 70 data format for serial peripheral interface (spi) instruction cclock synchronized sireal transfer (basic transfer) input instruction instruction code first transfer d15 d14 d13 d12 d11 d10 d9 d8 first transfer d7 d6 d5 d4 d3 d2 d1 d0 ib 0 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 8 ib 15 ib 14 ib 13 ib 12 ib 11 ib 10 ib 9 12 3 45 6 789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 lsb d15 rs 0 ?0? ?0? rs device i id code start byte index register set, instruction write msb sdi (input) scl (input) cs* (input) transfer start transfer en d d14 d4 d1 ?1? ?1? ?1? id d13 d12 d11 d10 d9 d8 d7 d6 d5 d3 d2 d0 HD66779 rev.1.00, june.13.2003, page 43 of 70 settings for data shift direction/boder mode the data shift direction is changeable by setting according to the panel size and the assembly. the border color control is only on the 6 channels (2rgbs) each at the left and right sides in de transfer mode. see page 53, ?system configuration example 4?. bmode 1 shl panel configuration example (without border) l l l h bmode 1 shl panel configuration example (with border) h l h h bmode2="h" bmode2="l" s360 s366 s366 tft panel 720ch (240rg b) 2line 2line chip top chip top s1 s1 s7 6ch (2rgb) 6ch (2rgb) bmode2="h" bmode2="l" s360 s366 s366 tft panel 720ch (240rg b) 2line 2line chip top chip top s1 s1 s7 6ch (2rgb) 6ch (2rgb) s366 s366 tft panel 720ch (240rg b) chip top chip top s7 s7 s360 s360 tft panel 720ch (240rg b) chip top chip top s1 s1 make settings for data shift direction & border mode only with pin settings possible possible make settings for data shift direction & border mode only with pin settings impossible impossible HD66779 rev.1.00, june.13.2003, page 44 of 70 lcd ac drive the HD66779 supports n-raster-row inversion ac drive to alternate signals by arbitrary n raster-rows, where ?n? is from 1 to 2, in addition to lcd inversion drive by frame. when deciding the number of ?n?, by which alternation occurs, with nw bit, check the quality of display on the actual lcd panel. if the number of raster rows for alternation is set small, the lcd alternation frequency becomes high and the charged/discharged current will increase on the lcd cell. frame ac waveform driving line ac waveform driving 1 frame 1 frame back porch front porch back porch front porch 1 2 3 4 1 2 3 4 1 2 321 322 321 322 336 336 ac point ac point ac poi nt 3 4 back porch two lines ac waveform driving HD66779 rev.1.00, june.13.2003, page 45 of 70 lcd display signal control the HD66779 allows selection of an optimum lcd display signal for the configuration of a system. see ?display signal select control? in the ?instruction? section, with regard to the timing of signal. register setting level shifter voltage output (vgh-vgl) logic voltage output (vcc-gnd) dsc1 dsc0 gif1 gif0 sout2 sout3 sout4 lsout2 lsout3 lsout4 0 0 ? ? ? ? ? ? 0 1 ? ? ? ? ? ? 1 0 ? ? ? ? ? ? 0 0 1 1 ? ? ? ? ? ? 0 0 line cycle clock 1 line cycle clock 2 ? ? ? ? 0 1 line cycle clock 1 line cycle clock 2 gate off signal ? ? ? 1 0 line cycle clock 1 line cycle clock 2 gate-all- on signal ? ? ? 0 1 1 1 line cycle clock 3 gate-all-on signal gate off signal ? ? ? 0 0 ? ? ? line cycle clock 1 line cycle clock 2 ? 0 1 ? ? ? line cycle clock 1 line cycle clock 2 gate off signal 1 0 ? ? ? line cycle clock 1 line cycle clock 2 gate-all-on signal 1 0 1 1 ? ? ? line cycle clock 3 gate all on signal gate off signal 0 0 line cycle clock 1 line cycle clock 2 ? line cycle clock 1 line cycle clock 2 ? 0 1 line cycle clock 1 line cycle clock 2 gate off signal line cycle clock 1 line cycle clock 2 gate off signal 1 0 line cycle clock 1 line cycle clock 2 gate all on signal line cycle clock 1 line cycle clock 2 gate-all-on signal 1 1 1 1 line cycle clock 3 gate-all-on signal gate off signal line cycle clock 3 gate-all-on signal gate off signal note) leave open for ???. HD66779 rev.1.00, june.13.2003, page 46 of 70 grayscale amplifier configuration the following figure illustrates the configuration of a grayscale amplifier. the input power into vref0p ~ vreff4p, vref0n ~ vref4n is divided internally with internal resistor of HD66779 to generate voltages from v0 to v63. control block v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 v32 v33 v34 v35 v36 v37 v38 v39 v40 v41 v42 v43 v44 v45 v46 v47 v48 v49 v50 v51 v52 v53 v54 v55 v56 v57 v58 v59 v60 v61 v62 v63 decoder decoder decoder decoder decoder decoder decoder vref0p vref0n v0amp vref4p vref4n v63amp vref1p vref1n v15amp vref2p vref2n v31amp vref3p vref3n v47amp output 36 66 grayscale generation portion note) electric potential must be supplied extern ally to all vref0p~vref4p, vref0n~vref4n. HD66779 rev.1.00, june.13.2003, page 47 of 70 the relationship between input data and output level the following figure shows the relationship between the pixel data and the source output level. 111111 pixel data (common to rgb pi xel) negative polarity positive polarity 0000 00 v63 v0 v15 v31 v48 negative polarity positive polarity voltage level vref4p vref0p vref1p vref2p vref3p vref4n vref0n vref1n vref2n vref3n output level source output and vcom positive polarity n egative polarity sn vcom source output level and pixel data HD66779 rev.1.00, june.13.2003, page 48 of 70 voltage calculation formula (positive polarity) gra y scale volta ge formula v0 vref0p v1 v15+(v0-v15)*(134/154) v2 v15+(v0-v15)*(124/154) v3 v15+(v0-v15)*(114/154) v4 v15+(v0-v15)*(104/154) v5 v15+(v0-v15)*(94/154) v6 v15+(v0-v15)*(84/154) v7 v15+(v0-v15)*(74/154) v8 v15+(v0-v15)*(64/154) v9 v15+(v0-v15)*(54/154) v10 v15+(v0-v15)*(44/154) v11 v15+(v0-v15)*(34/154) v12 v15+(v0-v15)*(25/154) v13 v15+(v0-v15)*(16/154) v14 v15+(v0-v15)*(8/154) v15 vrep1p v16 v31+(v15-v31)*(77/84) v17 v31+(v15-v31)*(70/84) v18 v31+(v15-v31)*(63/84) v19 v31+(v15-v31)*(57/84) v20 v31+(v15-v31)*(51/84) v21 v31+(v15-v31)*(45/84) v22 v31+(v15-v31)*(39/84) v23 v31+(v15-v31)*(34/84) v24 v31+(v15-v31)*(29/84) v25 v31+(v15-v31)*(24/84) v26 v31+(v15-v31)*(20/84) v27 v31+(v15-v31)*(16/84) v28 v31+(v15-v31)*(12/84) v29 v31+(v15-v31)*(8/84) v30 v31+(v15-v31)*(4/84) v31 vref2p v32 v48+(v31-v48)*(55/59) v33 v48+(v31-v48)*(51/59) v34 v48+(v31-v48)*(47/59) v35 v48+(v31-v48)*(44/59) v36 v48+(v31-v48)*(41/59) v37 v48+(v31-v48)*(38/59) v38 v48+(v31-v48)*(35/59) v39 v48+(v31-v48)*(32/59) v40 v48+(v31-v48)*(29/59) v41 v48+(v31-v48)*(26/59) v42 v48+(v31-v48)*(23/59) v43 v48+(v31-v48)*(20/59) v44 v48+(v31-v48)*(16/59) v45 v48+(v31-v48)*(12/59) v46 v48+(v31-v48)*(8/59) v47 v48+(v31-v48)*(4/59) v48 vref3p v49 v63+(v48-v63)*(85/89) v50 v63+(v48-v63)*(81/89) v51 v63+(v48-v63)*(77/89) v52 v63+(v48-v63)*(73/89) v53 v63+(v48-v63)*(69/89) v54 v63+(v48-v63)*(64/89) v55 v63+(v48-v63)*(59/89) v56 v63+(v48-v63)*(54/89) v57 v63+(v48-v63)*(48/89) v58 v63+(v48-v63)*(42/89) v59 v63+(v48-v63)*(35/89) v60 v63+(v48-v63)*(28/89) v61 v63+(v48-v63)*(21/89) v62 v63+(v48-v63)*(14/89) v63 vref4p n ote: the following relationship must be observed. ddvdh-0.3v>=vref0p>vref1p>vref2p>vref3p>vref4p>=gnd-0.3v ddvdh-0.3 v>=vref0n>vref1n>vref2n>vref3n>vref4n>=gnd+0.3v ddvdh-1.0v>=vref1p, vref1n vref3p, vref3n>=gnd+1.0v vn-vn-1>20mv(n=0-62) HD66779 rev.1.00, june.13.2003, page 49 of 70 voltage calculation formula (negative polarity) gra y scal vola ge formula v0 vref0n v1 v15+ (v0-v15) * (75/89) v2 v15+ (v0-v15) * (68/89) v3 v15+ (v0-v15) * (61/89) v4 v15+ (v0-v15) * (54/89) v5 v15+ (v0-v15) * (47/89) v6 v15+ (v0-v15) * (41/89) v7 v15+ (v0-v15) * (35/89) v8 v15+ (v0-v15) * (30/89) v9 v15+ (v0-v15) * (25/89) v10 v15+ (v0-v15) * (20/89) v11 v15+ (v0-v15) * (16/89) v12 v15+ (v0-v15) * (12/89) v13 v15+ (v0-v15) * (8/89) v14 v15+ (v0-v15) * (4/89) v15 vref1n v16 v32+ (v15-v32) * (55/59) v17 v32+ (v15-v32) * (51/59) v18 v32+ (v15-v32) * (47/59) v19 v32+ (v15-v32) * (43/59) v20 v32+ (v15-v32) * (39/59) v21 v32+ (v15-v32) * (36/59) v22 v32+ (v15-v32) * (33/59) v23 v32+ (v15-v32) * (30/59) v24 v32+ (v15-v32) * (27/59) v25 v32+ (v15-v32) * (24/59) v26 v32+ (v15-v32) * (21/59) v27 v32+ (v15-v32) * (18/59) v28 v32+ (v15-v32) * (15/59) v29 v32+ (v15-v32) * (12/59) v30 v32+ (v15-v32) * (8/59) v31 v32+ (v15-v32) * (4/59) v32 vref2n v33 v48+ (v32-v48) * (80/84) v34 v48+ (v32-v48) * (76/84) v35 v48+ (v32-v48) * (72/84) v36 v48+ (v32-v48) * (68/84) v37 v48+ (v32-v48) * (64/84) v38 v48+ (v32-v48) * (60/84) v39 v48+ (v32-v48) * (55/84) v40 v48+ (v32-v48) * (50/84) v41 v48+ (v32-v48) * (45/84) v42 v48+ (v32-v48) * (39/84) v43 v48+ (v32-v48) * (33/84) v44 v48+ (v32-v48) * (27/84) v45 v48+ (v32-v48) * (21/84) v46 v48+ (v32-v48) * (14/84) v47 v48+ (v32-v48) * (7/84) v48 vref3n v49 v63+ (v48-v63) * (146/154) v50 v63+ (v48-v63) * (138/154) v51 v63+ (v48-v63) * (129/154) v52 v63+ (v48-v63) * (120/154) v53 v63+ (v48-v63) * (110/154) v54 v63+ (v48-v63) * (100/154) v55 v63+ (v48-v63) * (90/154) v56 v63+ (v48-v63) * (80/154) v57 v63+ (v48-v63) * (70/154) v58 v63+ (v48-v63) * (60/154) v59 v63+ (v48-v63) * (50/154) v60 v63+ (v48-v63) * (40/154) v61 v63+ (v48-v63) * (30/154) v62 v63+ (v48-v63) * (20/154) v63 vref4n n ote: the following relationship must be observed. ddvdh-0.3v>=vref0p>vref1p>vref2p>vref3p>vref4p>=gnd- 0.3v ddvdh-0.3 v>=vref0n>vref1n>vref2n>vref3n>vref4n>=gn d- 0.3v ddvdh-1.0v>=vref1p, vref1n vref3p, vref3n>=gnd-1. 0v vn-vn+1>20mv(n=0-62) HD66779 rev.1.00, june.13.2003, page 50 of 70 system configuration examples system configuration example 1 240(horizontal) x 320(vertical) pixels only with pin settings, no spi the following figure illustrates an example of adopting HD66779 for tft-lcd panel with an incorporated gate driver. 2line 2(rgb) 2lin e 720ch(240rgb) x320line tft-lc d 720ch(240rgb) 320line 6ch 2(rgb) 6ch shift register internal gate driver circuit HD66779 HD66779 366ch 366ch sout1/2/3 vcoms vgh/vgl e102 e101 vgh/vg l vcom adjustm ent vgh/vgl ddvdh/agnd vcc/gnd vref0-4p vref0-4n vcom r lcd drive power supply circuit vsync hsync enable dotclk pd17-0 processor HD66779 rev.1.00, june.13.2003, page 51 of 70 system configuration example 2 240(horizontal) x 320(vertical) pixels with spi the following figure illustrates an example of adopting HD66779 for tft-lcd panel with an incorporated gate driver. 2line 2(rgb) 2lin e 720ch(240rgb) x320line tft-lc d 720ch(240rgb) 320line 6ch 2(rgb) 6ch shift register internal gate driver circuit HD66779 HD66779 366ch 366ch sout1/2/3 vcoms vgh/vgl e102 e101 vgh/vg l vcom ad j ustmen t vgh/vgl ddvdh/agnd vcc/gnd vref0-4p vref0-4n vcom r lcd drive power supply circuit vsync hsync enable dotclk pd17-0 application processor base band processor cs scl sdi HD66779 rev.1.00, june.13.2003, page 52 of 70 system configuration example 3 120(horizontal) x 160(vertical) pixels only with pin settings, no spi the following figure illustrates an example of adopting HD66779 for tft-lcd panel with an incorporated gate driver. 360ch (120rgb) x 160line tft-lc d 360ch(120rgb) shift register internal gate driver circuit HD66779 360ch sout1/2/3 vcoms vgh/vg l vcom adjustmen vgh/vgl ddvdh/agnd vcc/gnd vref0-4p vref0-4n vcom r lcd drive power supply circ uit vsync hsync enable dotclk pd17-0 processo r 160line HD66779 rev.1.00, june.13.2003, page 53 of 70 system configuration example 4 120(horizontal) x 160(vertical) pixels only with pin settings, de transfer mode the following figure illustrates an example of adopting HD66779 for tft-lcd panel with an incorporated gate driver. note 1) the border color control while using de transfer mode is on the 6 channels each at left and right side. note 2) the border color in de transfer mode is only black and white to be switched with bmode3 pin. 2(rg b) 720ch(240rgb) x320line tft-lc d 720ch(240rgb) 320line 6ch 2(rgb) 6ch shift register internal gate driver circuit HD66779 HD66779 366ch 366ch sout1/2/3 vcoms vgh/vgl e102 e101 vgh/vg l vcom adjustm ent vgh/vgl ddvdh/agnd vcc/gnd vref0-4p vref0-4n vcom r lcd drive power supply circuit enable (de) dotclk (mclk) pd17-0 processor bmode3 bmode3 bd control bmode 3 HD66779 rev.1.00, june.13.2003, page 54 of 70 system configuration example 5 240(horizontal) x 320(vertical) pixels only with pin settings, de transfer mode the following figure illustrates an example of adopting HD66779 for tft-lcd panel with an incorporated gate driver. note 1) the border color control while using de transfer mode is on the 6 channels each at left and right side. note 2) the border color in de transfer mode is only black and white to be switched with bmode3 pin. 2(rg b) 720ch(240rgb) x320line tft-lc d 720ch(240rgb) 320line 6ch 2(rgb) 6ch HD66779 HD66779 366ch 366ch vgh/vgl e102 e101 vgh/vg l vgh/vgl ddvdh/agnd vcc/gnd vref0-4p vref0-4n vcom r lcd drive power supply circuit enable (de) dotclk (mclk) pd17-0 processor bmode3 bmode3 bd control bmode 3 hd66312 192 ch d101 0eb cl d102 192 ch hd66312 d101 0eb cl 128 ch 192 ch vcom adjustment vcoms lsout4 lsout2 lsou t1 HD66779 rev.1.00, june.13.2003, page 55 of 70 vcom generation vcom is generated from vcomr, a reference voltage of vcom, by coupling method with an external circuit, which is supplied with the tft display common electrode. vcom output am plifier ddvdh vcomrc vcom s vcom p1 r2 r1 ddvdh c1 vcom r 0v vcoms vcom center=p1 ddvdh vcom r note 2 c2 note 2 note 3 note 3 note 1 note 1) the relationship vcomr =< ddvdh - 0.3v must be observed. note 2) use c1 = c2, 1 f =< c1(c2) as a standard setting. an appropriate value can be set according to the load capacity of the panel. note 3) use r1+r2 =< 100 ? as a standard setting . an appropriate value can be set according to the load capacity of the panel. the external capacitor ?c1? must be lowered to gnd when vcoms is halted. HD66779 rev.1.00, june.13.2003, page 56 of 70 voltage application and insulation sequence the voltage application/insulation sequence illustrated as follows must be observed. (1) (1) (1) (2) (1) (1) (2) (1) vgh vgh ddvdh ddvdh vcc, in vcc, in vgl vgl (1) = 5ms (min.) ( 2 ) = 10ms ( min. ) gn d HD66779 rev.1.00, june.13.2003, page 57 of 70 absolute maximum ratings items symbol unit rated value notes power supply voltage (1) vcc v - 0.3 ~ +4.3 (1), (2) power supply voltage (2) ddvdh-gnd v - 0.3 ~ + 6.0 (1), (3) power supply voltage (3) vgh- agnd v - 0.3 ~ + 22.0 (1), (4) power supply voltage (4) agnd- vgl v - 0.3 ~ + 16.5 (1), (5) input voltage vt v - 0.3 ~ vcc + 0.3 (1) operational temperature topr oc - 40 ~ +85 (1), (6) storage temperature tstg oc - 55 ~ +110 (1) note1: if the lsi is used above these absolute maximu m ratings, it may be permanently damaged. using the lsi within the limit of electrical characteristics is strongly recommended during normal operation. the use of lsi under a condition above the limit may lead to malfunction and loss of credibility of lsi. note2: vcc (high) gnd (low) must be observed. note3: ddvdh (high) gnd (low) must be observed. note4: vgh (high) agnd (low) must be observed. note5: agnd (high) vgl (low) must be observed. note6: the dc/ac characteristics of die a nd wafer products is guaranteed at 85 oc. HD66779 rev.1.00, june.13.2003, page 58 of 70 electrical characteristics dc characteristics vcc = 2.5v ~ 3.6v, ta = -40oc ~ +85oc: see note 1 items symbol unit measurement condition min. typ. max. notes input ?high? level voltage v ih v vcc = 2.5v ~ 3.6v 0.7vcc ?? vcc (2),(3) input ?low? level voltage v il v vcc = 2.5v ~ 3.6v -0.3 ?? 0.15vcc (2),(3) output ?high? level voltage v oh v ioh = -0.1ma 0.7vcc ?? ?? (2) output ?low? level voltage v ol v iol = 0.1ma ?? ?? 0.15vcc (2) input/output leak current i li a vin = 0 ~ vcc -5 ?? 5 (4) normal operation mode i op ma vcc = 3v, ddvdh = 5h, vgh = 12v, vgl = -8v, dotclk = 8mhz, 1h period = 4 5 s, 366ch ta = 25oc ?? 1.1 1.35 (5) current consumption (vcc ~ gnd) static state i st a vcc = 3v, ddvdh = 5v, vgh = 12v, vgl = -8v, dotclk = 8mhz, 1h period = 4 5 s, 366ch ta = 25oc ?? 5 10 (5) ddvdh ? agnd i ddp ma vcc = 3v, ddvdh = 5v, vgh = 12v, vgl = -8v, dotclk = 8mhz, 1h period = 4 5 s, 366ch ta = 25oc ?? 1.7 1.9 (5) lcd power supply voltage (ddvdh ~ agnd) agnd ? vgl i vlp a vcc = 3v, ddvdh = 5v, vgh = 12v, vgl = -8v, dotclk = 8mhz, 1h period = 4 5 s, 366ch ta = 25oc ?? 80 110 (5) HD66779 rev.1.00, june.13.2003, page 59 of 70 items symbol unit measurement condition min. typ. max. notes lcd power supply voltage (ddvdh ~ agnd) vgh - agnd i vhp a vcc = 3v, ddvdh = 5v, vgh = 12v, vgl = -8v, dotclk = 8mhz, 1h period = 4 5 s, 366ch ta = 25oc ?? 80 110 (5) output voltage difference ? vo mv ?? ?? +/-15 +/-25 (7) average output voltage fluctuation ? v ? mv ?? ?? +/-15 ?? (8) HD66779 rev.1.00, june.13.2003, page 60 of 70 serial peripheral interface timing characteristics vcc = 2.5 ~ 3.6 v item symbol unit timing diagram min typ max serial clock cycle time t scyc s figure 1 0.2 ? 40 serial clock ?high?-level pulse width t sch ns figure 1 80 ? ? serial clock ?low?-level pulse width t scl ns figure 1 80 ? ? serial clock rise/fall time t scr, t scf ns figure 1 ? ? 40 chip select set up time t csu ns figure 1 40 ? ? chip select hold time t ch ns figure 1 120 ? ? serial input data set up time t sisu ns figure 1 60 ? ? serial input data hold time t sih ns figure 1 60 ? ? reset timing characteristics v cc = 2.5 to 3.6 v item symbol unit timing diagram min typ max reset ?low?-level width t res ms figure 2 1 ? ? reset rise time t rres s figure 2 ? ? 10 rgb interface timing characteristics rgb interface, vcc = 2.5v ~ 3.6v item symbol unit timing diagram min. typ. max. vsync/hsync set up time tsyncs ns figure 3 20 ? enable set up time tens ns figure 3 30 ? ? enable hold time tenh ns figure 3 30 ? ? dotclk ?low?-level pulse width pw dl ns figure 3 40 ? ? dotclk ?high?-level pulse width pw dh ns figure 3 40 ? ? dotclk cycle time tcycd ns figure 3 100 ? ? data set up time tpds ns figure 3 30 ? ? data hole time tpdh ns figure 3 30 ? ? dotclk, vsync, hsync rise/fall time trgbr, trgbf ns figure 3 ? ? 25 HD66779 rev.1.00, june.13.2003, page 61 of 70 switching characteristics rgb interface, vcc = 2.5v to 3.6 v item symbol unit timing diagram min. typ. max. start pulse set up time tsws ns figure 4 20 ? ? start pulse delay time tswo ns figure 4 ? ? 80 lcd driver output characteristics item symbol unit test condition min. typ. max. note driver output delay time tdd s vcc = 3v, ddvdh = 5v, vgh = 8v, vgl = 0v, ta = 25oc, dotclk = 8mhz, all pins undergo a same change from same grayscale level time required to reach +/- 25 mv during vcoms polarity change load resistance r = 10k ? , load capacity 50pf ? 20 35 (10) HD66779 rev.1.00, june.13.2003, page 62 of 70 notes to electrical characteristics 1. the dc/ac electrical characteristics of bare die and wafer products are guaranteed at 85 c. 2. the following figures illustrate the configurations of i pin, i/o pin, and o pin. input pin pmos n mos vcc gnd vcc pmos n mos gnd output pin pmos output data output en able (input circuit) vcc n mos (tri-state output circuit) vcc pmos n mos gnd input/output pins HD66779 rev.1.00, june.13.2003, page 63 of 70 3. test, im1, im0/id pins must be grounded or connected to vcc. 4. this excludes the current through output drive mos. 5. this excludes the current through the input/output units. the input level must be fixed to a certain level because penetrating current increases in the input circuit when cmos input level takes a middle level. the current consumption is unchanged irrespective of ?high? or ?low? of cs*pin while the HD66779 is not accessed through interface pins. 6. the relationship between operational condition and current consumption is as follows. 4.0 4.5 5.0 i ddp (ma) vcc = 3v, dotclk = 8mhz, ta = 25 degree centigrade 1.9 1.8 1.7 1.6 1.5 1.4 3.5 5.5 7. the output voltage difference is the difference in the neighboring output voltages for a same display (within a chip). the output voltage difference in offset cancel operation is within +/- 10mv. 8. the average output voltage fluctuation is the difference in the average output voltages among different chips. the average output voltage is an average voltage within a chip for a same display. this value is just for a referential purpose. 9. this applies to the case when clocks are supplied externally. duty = th 100% th+ tl x t rcp t th 0.7vcc 0.5vcc 0.3vcc fcp tl 10. the lcd driver output delay time depends on the load on the lcd panel. check the quality of display on the actual lcd panel before making settings for the frame frequency and one-line cycle. HD66779 rev.1.00, june.13.2003, page 64 of 70 lcd driver output delay time tdd ( s) 30 50 70 referential data (typ) 16.0 20.0 24.0 load capacity c (pf) test point 50 p f data bus: pd17-0 load circuit for ac characteristics mesurement load circuit for lcd driver output characteristics measuremen t lcd output : s1-s366 load resistance r load capacity c test point HD66779 rev.1.00, june.13.2003, page 65 of 70 timing diagram serial peripheral interface operation tsch tsisu tscr vih vil vih vil vih vil tch vih vil vih vil tscl tsih vil tscyc input data vih start: s e nd: p tscf vih cs* scl sdi vil vil input data tcsu figure 1 reset operation rese t* t res v il tr res v il v il figure 2 HD66779 rev.1.00, june.13.2003, page 66 of 70 interfacing operation vsync hsync enable dotclk pd17-0 tsyncs tenh tens tpdh tpds pwdh pwdl trgbf trgbf trgbf trgbr write data vih vil vih vil vih vil vih vil vih vil vih vil vih vil vih vil vih vil vih vil vih vil vih vil vih vil tcycd straight line : epl = "h" dotted line : epl = "l" vih vil vih vil vil vih straight line : dpl = "h" dotted line : dpl = "l" figure 3 switching operation eio output from master side dotclk vih vil vih vil vih vil vih vil vih vil vil vih voh vol vih vil tswo tsws straight line : dpl = "h" dotted line : dpl = "l" eio input from slave side figure 4 HD66779 rev.1.00, june.13.2003, page 67 of 70 lcd driver output characteristics vcom s1-366 tdd designated grayscale voltage +/-25mv figure 5 HD66779 rev.1.00, june.13.2003, page 68 of 70 keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but ther e is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation p roduct best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporat ion or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party's rights, origin ating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reas ons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest produ ct information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracie s or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas te chnology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp oration assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used un der circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor wh en considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or u ndersea repeater use. 6. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lic ense from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com copyright ? 2003. renesas technology corporation, all rights reserved. printed in japan. colophon 0.0 HD66779 rev.1.00, june.13.2003, page 69 of 70 revision record rev. date page contents of modification approved by 0.2 2002.10.25 first issue 0.3 2002.12.13 4 figure 1: change ?pos? to ?testps? 5 change the explanation for (1) external display interface. 6 add ?testps? to talbe 1. 7 add ?when using border display, display period is 320h.? to function of bmode1. delete ?pos? from table 1. 8 change function of dotclk. add ?(de)? to the signal name ?enable?. add ?when using de transfer mode (ssmd1 = ?h?), bp setting is invalid.? to function of bp. 10 change function of gaon. 12 revise pad arrangement figure to rev.0.1. 13 revise pad coordinate (input) to rev. 0.1. 15 delete ?pos? from figure 5. delete the explanation of ?pos?. 17 change ?14 lines>=bp>=2 lines? in the explanation of bp3-0 to ?14 lines >= number of back porch lines minus number of border lines?. 19 change the waveform of sout4 upside down in figure 12. chage the note added to figure 12. 20 add a note ?? to the explanation of fhn. 21 delete ?*pos? and ?0? in bit 9 of r01h, and add ?1? instead of ?pos?. 22 delete ?source output: s1 - s366 output ?gnd? level? from 2. initial level of output pin. 24 change figure 16 and its note. 25 delete the explantion of ?power save function (pos)?. change figure 18. 26 delete table 13 and add new table 13, 14, and 15. 29 add ?for the detail setting of timing, refer to ?signal timing control function for lcd display? to figure 21. 30 add the same note added to figure 21 to figure 22. 33 add the same note added to figure 21 to figure 25. 34 add the same note added to figure 21 to figure 26. 35 add the same note added to figure 21 to figure 27. 40 delete table 17(old) wire setting. 40 correct table 18. HD66779 rev.1.00, june.13.2003, page 70 of 70 rev. date page contents of modification approved by 0.3 2002.12.13 51 correct ?vcc? to ?vcc, in? in figure 44. 53 change table 22. (t.b.d decided) 54 change table 23 and 24. (t.b.d decided) 55 change talbe 24, 25, and 26. (t.b.d decided) 57 correct ?+/- 2m? to ?+/- 10m? in note 7. 60 change figure 56 and 57. 1.0 2002.6.13 9 error correction. change ?gnd? to ?vcc? to which test4 is connected. change ?test1, 4-15? to ?test1, 5-15? and number of pins from ?15? to ?14?. addition to function column. ?make sure vgh ddvdh vcc? 5, 14, 19, 26, 32~35, 54, 57 error corrections 58, 60, 61, 63, 64, 67 addition of measurement to the electrical characteristics tables w here marked with ?tbd?. |
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